March 1 - 4, 2027 | Santa Clara, CA, United States

DVCon U.S. 2027

DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well as general purpose languages such as C, C++, Python, PERL and Tcl. Tools and methodologies include the use of artificial intelligence, machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP-based SoC design methods, reference flows and Mixed Signal design and verification.

Call for Extended Abstracts

Abstract Submission Deadline: September 7, 2026

The Design & Verification Conference is looking for submissions for the in-person 2027 Conference and Exhibition. This conference focuses on the practical aspects of design and verification of electronic systems and integrated circuits. This could be applications of languages, tools, methodologies, and/or standards. This could be your chance to help the industry we are all a part of. For those familiar with DVCon, the submission timeline has changed for this year. Please see below for more details.

DVCon honors the Stuart Sutherland Best Paper Award. The awards will be selected by the attendees at DVCon, based on the quality of both the paper and their presentation. Awards will be offered for both slide and poster presentation formats. So please submit your abstract and join DVCon U.S. 2027!

Please submit your extended abstract outlining your proposed presentation by Monday, September 7.

Download the Call for Extended Abstracts strings.external_link

Submission Topics

  • coverage closure

  • analysis techniques

  • machine learning-guided coverage

  • test efficiency

  • scalable formal methods

  • assertion-driven flows

  • formal applications

  • methodology

  • clock/reset-domain crossing techniques

  • timing constraints

  • asynchronous logic

  • domain verification

  • UVM design patterns

  • reuse strategies

  • SoC testbenches

  • Python/C++ co-simulation

  • DPI

  • PSS

  • ISO 26262

  • DO-254

  • fault injection

  • safety coverage

  • verification metrics

  • RISC-V cores

  • custom instruction set architecture extensions

  • compliance testing

  • microarchitecture verification

  • side-channel analysis

  • data leakage prevention

  • secure boot

  • hardware trust modeling

  • automation pipelines

  • debug triage

  • result clustering

  • cloud flows

  • DevOps/GitOps for verification

  • spec-to-test traceability

  • audit readiness

  • natural language processing tools

  • requirements-driven verification

  • analog/mixed-signal integration

  • RNMs, co-simulation with digital

  • behavioral modeling

  • UPF methodologies

  • dynamic power-aware simulation

  • power state modeling

  • assertions

  • pre-silicon validation with FPGA

  • hybrid flows

  • debug methodologies

  • integration challenges

  • hardware/software co-verification

  • pre-silicon debug

  • SoC bring-up

  • software development

  • virtual prototyping

  • packaging

  • generating and verifying multiple configurations

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