Tutorial sponsored by:

Organizers: Francine M. Bacchini - Francine Bacchini , Inc.
Presenters: Lawrence Loh - Jasper Design Automation, Inc.
Mercedes Tan - Sun Microsystems
Jay Littlefield - Jasper Design Automation, Inc.

The face of verification is changing.  Simulation and random testbenches alone cannot ensure sufficient confidence in the design implementation.  Even the benefits of incremental solutions such as assertion-based verification (ABV) have not managed to keep pace with increasing design complexity.  Formal verification promises the benefits of exhaustive verification confidence, and, with the proper methodology, most any verification team today can benefit from exhaustive verification of complex block specifications, interface protocols, and standard bus interfaces.

This half-day tutorial is aimed at hardware design and verification engineers, CAD teams, and managers interested in understanding the benefits and challenges present in effectively leveraging a formal strategy within their production verification environment.  The tutorial cuts through the confusion and mixed messaging about what formal verification is and what it can accomplish on real designs, and introduces a production-proven verification environment combining pure formal exhaustive proofs and existing simulation resources.  This combination provides maximum confidence and measurable quality improvements over typical verification flows.

The tutorial begins with an overview of the benefits and challenges, both technical and business, of integrating formal into an existing verification environment.  Attendees will be introduced to the most effective techniques for converting a design specification into a verification plan that includes formal verification.  Issues and techniques for dealing with coverage concerns when integrating formal verification will be reviewed.  Sun Microsystems will discuss the real world challenges faced with accurate coverage tracking and strategies for combining results from different technologies.

The presenters include top formal verification experts with multiple hands-on design experience and end users who have successfully used the methodologies presented on some of the today’s most complex designs projects.