Tutorial sponsored by:

Organizer: Synopsys, Inc.
Presenters: Srinivasan Venkataramanan - Synopsys, Inc.
Ben Cohen - Vhdlcohen Publishing
Ajeetha Kumari - Contemporary Verification Consultants

The Verification Methodology Manual (VMM) for SystemVerilog provides a proven, robust and scalable approach for building advanced verification environments. It captures years of industry best-practices for taking advantage of constrained-random, coverage-driven and assertion-based verification. However, absorbing all of this information can be a daunting task for engineers coming from a traditional directed-test verification background. This tutorial will present a pragmatic approach to VMM methodology adoption, guided by practical examples and straightforward explanations.
Attendees will learn how to build a VMM-compliant testbench. The tutorial will present by example the development of transactions and channels; the atomic transaction generator; the use of SystemVerilog interfaces; the command transactor and monitor; the environment and testbench; the factory pattern. We will also explain how callbacks notifications can be used for the collection of coverage, for scoreboarding, and for the application of assertions that use class and interface variables. We will also explain by example the power of VMM for the definition of the scenario generators, and the application of schedulers and broadcasters.

Industry praise and support of the Verification Methodology Manual (VMM) for SystemVerilog, co-authored by ARM and Synopsys, has steadily increased since its introduction. Widespread adoption and user success has established the VMM as the industry's most robust and proven methodology for SystemVerilog. This tutorial is targeted at engineers and managers interested in adopting SystemVerilog for advanced functional verification.