Tutorial sponsored by:

Organizer: Michal Siwinski- Cadence Design Systems, Inc.
Presenter: Lovleen Bhatia - Texas Instruments Inc.
Erich Marschner - Cadence Design Systems, Inc.
Faisal Haque - Verification Central
Raghavan Menon - Ingot Systems, Inc.
Jon Michelson - Verification Central
Axel Scherer - Cadence Design Systems, Inc.

This half-day tutorial shows designers, verification engineers, and their management how to accelerate project schedules and improve product quality through the use of assertion-based verification (ABV) and formal analysis. Starting from the original verification plan, these techniques enable more thorough verification early in the development process, efficient reuse during the later stages of verification, and effective metrics to help determine when it is time to tape out.

The ABV methodology discussed in this tutorial spans block-level verification, chip-level simulation, and hardware acceleration/emulation. Attendees will learn how to apply the right verification technologies at the right phases of the development process to get the best results with the least amount of time and effort, thus providing the highest return on investment. The focus is on practical deployment of these technologies, leveraging real-world experience to explain where they add value and where they are less productive.

Because formal analysis may be relatively new to many attendees, this tutorial covers use of this technique in detail. Formal analysis can be used by designers early in the verification process to make their blocks robust before chip-level integration. Several distinct applications of formal technology, including interface protocol compliance verification, block-level bring-up, designer-level analysis, and verification-level analysis, are described in detail.

The presenters include industry authorities on assertions and formal analysis, EDA experts who have helped thousands of engineers succeed with these techniques, and end users who discuss their experiences on large development projects. Attendees should have a basic understanding of assertions and how they are specified. Detailed knowledge of specific assertion formats or previous experience with formal analysis is not required to benefit from the techniques and applications covered in this tutorial.