Session 6 • Friday, February 23, 2007
Rm: Cascade Ballroom
10:30 am - 12:00 pm
Formal Verification
Session Chair: Jayaram Bhasker - eSilicon Corp.

6.1 Benevolently Equivalent: Effective Usage Models for Logic Equivalence in Your Design Flow
Amit Chowdhry - Advanced Micro Devices

6.2 FEV's Greatest Bloopers: False Positives in Formal Equivalence
Erik Seligman, Joonyoung Kim - Intel Corp.

6.3 Complete Formal Verification of TriCore2 and Other Processors
Adriana Maggiore - OneSpin Solutions GmbH