Embedded Tutorial 3 • Friday, February 23, 2007
Rm: Siskiyou Ballroom
3:30 pm - 5:00 pm
Re-usable Performance Verification of Interconnect IP Designs

Sriram Swaminathan, K. Yogendhar, Vidhya Thyagarajan - Rambus Chip Technologies India (Pvt.) Ltd.

This tutorial discusses the importance of performance verification in the early stages of the design cycle to avoid re-spins due to performance issues. The paper focuses on reusable third-party design IPs and describes the challenges involved in verifying a configurable interconnect IP for performance and presents a case study of performance analysis setup for a PCI Express IP based system. The case study presents a configurable and re-usable performance verification setup and how various performance metrics such as roundtrip latency and bandwidth can be used to characterize an IP.