Conference on Using Hardware Design and Verification Languages DVCon is the premier conference on the application of languages, tools and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is on the usage of specialized design and verification languages such as Verilog, SystemVerilog, VHDL, PSL SystemC, e, and VERA, as well as general purpose languages such as C and C++. Tools and methodologies include the use of testbench automation,hardware- assisted verification, hardware/software co-verification, assertion-based and formal verification, and transaction-level system design and verification.

Who Attends DVCon
Conference attendees are promarily designers of electronic systems, ASICs and FPGAs, as well as those involved in research, development, and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature, and reflect real life experiences in using these languages and tools.