| Attendees are the judges for the Design and Verification Best Papers at the conference.
There is a $1000 prize for each category.
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2006 Recipients
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Session 4 - SystemVerilog in Action
Paper 4.3 - Guidelines for Creating a Formal Verification Testplan
Harry D. Foster - Mentor Graphics Corp.
Lawrence Loh, Vigyan Singhal - Jasper Design Automation, Inc.
Bahman Rabii - Google |
| 2006 Recipients |
Session 9 - Innovative Verification Solutions
Paper 9.1 - Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions
Mark Litterick - Verilab GmbH |
| Verification Area - 2005 Recipients |
Session 3 - Innovative Verification Solutions
Paper 3.3 - Using MatLab and Simulink in a SystemC Verification Environment
Jean Francois Boland - McGill Univ., Montreal, Quebec, Canada
Claude Thibeault - Ecole de Technologie Superieure. Montreal, Quebec, Canada
Zeljko Zilic - McGill Univ., Montreal, Quebec, Canada |
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Design Area - 2005 Recipients
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Session 10 - SystemVerilog in Action
Paper 10.2 - Using SystemVerilog Now with DPI
Rich Edelman, Doug Warmke - Mentor Graphics Corp., San Jose, CA |
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Verification Area - 2004 Recipients
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Session 2 - Coverage and Assertion-Based Verification
Paper 2.3 - Coverage-Based DV from Testplan to Tapeout using Random Generation and RTL Assertions
Carey Kloss, Dean Chao - Cisco Systems, San Jose, CA
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Design Area - 2004 Recipients
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Session 1 - Real World Design
Paper 1.1 - Design and Verification of a DSP using VHDL, Verilog, SystemC, and C++
Greg Tumbush, Bill Dittenhofer - Starkey Labs, Colorado Springs, CO |
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