| As design blocks become larger and more complex, assertion-based verification becomes the key for addressing Functional Verification -- one of the major bottlenecks of the entire design process. To maximize productivity, assertion-based verification requires the combination of powerful, yet easy-to-adopt, assertion language and a comprehensive proven methodology. The industry standards body, Accellera, has standardized the SystemVerilog hardware description and verification language, which includes powerful, expressive, and easy-to-learn assertion constructs that are aimed at specifying design intent. SystemVerilog enables full interoperability between design, assertions and testbench to provide the most effective assertion language for the RTL design community.
In this tutorial we present the use and benefits of assertion-based verification, showing how to effectively write assertions with SystemVerilog to verify a real and complex system-on-chip (SoC) logic block. While addressing practical issues to familiarize the audience with assertion-based verification best practices, we will use simulation and RTL hybrid formal verification to stress test the design and its interface to maximize the impact of assertion-based verification on overall verification productivity. This tutorial will show RTL and assertion code, and configuration files for the Synopsys VCS® complete RTL verification solution and Magellan™ hybrid formal verification.
Presenters:
- Ben Cohen - VhdlCohen Publishing, Palos Verdes Peninsula, CA
John Girard - Synopsys, Inc., Marlboro, MA
Jin Hou - Synopsys, Inc., Hillsboro, OR
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