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Tuesday, February 15, 2005
10:30 AM - 12:00 PM • Donner Ballroom
Session 2 - Arithmetic Modeling & Design
2.1 Signed Arithmetic in Verilog 2001 - Opportunities and Hazards
Greg Tumbush - Starkey Labs, Colorado Springs, CO

2.2 Fixed- and Floating-Point Packages for VHDL 2005
David Bishop - Eastman Kodak Co., Rochester, NY

2.3 At Last! -- A New Ultimately Flexible Discrete Convolution Architecture (Maybe): It’s Design and Validation
J. Robert Heath, Albert T. Wong - Univ. of Kentucky, Lexington, KY
Michael Lhamon - Lexmark International, Inc., Lexington, KY