ABOUT ACCELLERA

To improve designers' productivity, the electronic design industry needs a methodology based on both worldwide standards and open interfaces. Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International to focus on identifying new standards, development of standards and formats, and to foster the adoption of new methodologies.

Accellera's mission is to drive worldwide development and use of standard required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. Its Board of Directors guides all the operations and activities of the organization, and is comprised of representatives from ASIC manufacturers, systems companies and design tool vendors.

Membership

Accellera's members directly influence development of the most important and widely used standards in electronic design. Members' companies protect and leverage their investment in design languages through their funding of a proven, effective and responsible organization. In addition, Accellera members have a higher level of visibility in the EDA industry as active participants in Accellera-sponsored activities and as contributors to its decisions which impact the EDA industry

The Users Forum Committee drives the promotion and use of Accellera's language standards by holding workshops and the annual Design Verification Conference and Exhibition (formerly HDLCon).

Technical Committees

The Accellera Board of Directors established the Technical Committee (TC) to develop, update and extend hardware design language (HDL) standards. The TC is comprised of subcommittees that focus on the various standards under development and report to the TC Chair. In addition, Accellera supports the activities of certain IEEE working groups and cooperates with other standards groups within the EDA industry.

Technical Subcommittees:

HDL Interoperability
IEEE 1364 Standard for Verilog HDL
IEEE 1076 Standards for VHDL
IEEE 1481 Delay & Power Calculation Language
Design Constraints (DCDL)
Architectural Language
Verilog-AMS (Analog & Mixed-Signal)
IEEE 1364.1 Synthesis Interoperability
Advanced Library Modeling (ALF)
IEEE P1491 Standard Delay Format (SDF)
Verilog Formal Verification
System-Level Design Language (SLDL)
VITAL
Open Modeling Interface

More information about Accellera, including a membership application, can be found at www.accellera.org, or call (408) 358-9510.