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Wednesday, March 3, 2004
1:30 PM - 3:30 PM
Session 8 - Language Evolution and Verification
8.1 Achieving Design Verification closure of a Digital Signal Processor without HVLs!!
Ananth Nivarti, Sourav Roy, Ashok Balivada, Tushar Ringe, Raman Kumar, Rajiv Nadig - Analog Devices, Bangalore, India

8.2 Verification Applications of Aspect-Oriented-Programming (AOP)
Atsushi Kasuya, Ennis Hawk - Jeda Technologies, Inc., Mountain View, CA

8.3 Adopting SystemVerilog in a VHDL Flow
 Tom Fitzpatrick - Synopsys, Inc., Groton, MA
Cliff Cummings - Sumburst Design, Inc., Beaverton, OR

8.4 Improving Design and Verification Productivity with VHDL-200x
Stephen Bailey - Model Technology, a Mentor Graphics Co., Longmont, CO
Erich Marschner - Cadence Design Systems, Inc., Ellicott City, MD
Jim Lewis - SynthWorks Design, Inc., Tigard, OR
Jayaram Bhasker - eSilicon, Allentown, PA
Peter Ashenden - Ashenden Designs Pty Ltd., Stirling, SA Australia