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| Wednesday, March 3, 2004 |
1:30 PM - 3:30 PM
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| 7.1 Experiences of Modeling Soft IP’S at High Level of Abstraction Using SystemC: A Case Study Surya Jayadevappa, Imad Mahgoub - Florida Atlantic Univ., Boca Raton, FL 7.2 High Throughput Mixed-Signal Verification Techniques in VHDL 7.3 Doing Behavioral Design The Right Way Minimizes Verification 7.4 A Guide to Building Faster Simulation Farms: It’s Not Just the CPU Clock Speed |
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