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| DVCon 2003 will have one of the most exciting and technical programs in the conference's 10 year history. The call for papers for this conference received a large number of high quality, technical proposals, on a wide range of engineering topics. The selected papers will be presented in six sessions. Some sessions will focus on the usage and new developments of Hardware Description Languages (HDLs). Other sessions are focused to Hardware Verification Languages (HVLs). We received so paper proposals on experiences in design verification, such as the usage of assertions, that two paper sessions are dedicated for engineers to share those experiences.
In addition to the 38 technical papers, the program includes 3 exciting panels on HDL and HVL topics. The last day of the conference offers 7 excellent tutorials to choose from. The tutorials are presented by true industry experts and provide a cost effective forum for learning new tricks in design and verification. They keynote luncheon address will be equally valuable. Aart De Geus, CEO of Synopsys, will share his vision of a new engineering paradigm, "Correct by Verification". As you review the paper, panel and tutorial titles below, I am confident you will find a number of topics that will be valuable in current and future projects. You may even want to have an associate attend the conference as well, so that you can each attend different sessions and double the information you bring back to your company! I look forward to seeing you at DVCon 2003! Stuart Sutherland, Program Chair |