DVCon (formerly called HDLCon) is the premier conference on the usage of Hardware Description Languages (HDLs), and Hardware Verification Languages (HVLs) for the design and verification of electronic systems and integrated circuits. The focus of the conference is on specialized languages such as VHDL, Verilog, SystemVerilog, SystemC, SUPERLOG, e and VERA, as well as general purpose languages such as C, and C++. Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of Electronic Design Automation (EDA) tools.

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DVCon 2004 Call for Papers is available.

"Chip Architects Can Audit a Design to Asses and Even Reduce Random Testing" by Dan Joyce, Raymond Harlan and Ramon Enriquez, Hewlett-Packard Co., Austin, TX

Honorable Mentions: (best rated paper in each session):

"Establishing Common Semantics to Link Testbenches and Assertions in SystemVerilog 3.1" by Tom Fitzpatrick, Peter Flake, Arturo Salz, Phil Moorby and Surrendra Dudani, Synopsys, Inc.

"The Impact of Synthesis on Design Closure--OR--The Netlist Matters!, by Chi-Ping Hsu, Pradeep Fernandes and Steve Carlson, Get2Chip Inc.

"Creating Useful Coding Guidelines for a Verification Environment", by Ambar Sarkar, Paradigm Works Inc.

"VHDL--The Verification Tool You Didn't Know You Had", by David Smith, Intel Corporation

"HEX: A Multi-threaded Verification Environment for an ARM System On A Chip", by Jeff Breti, Mint Technology, a division of LSI Logic