HIGHLIGHTS IN THIS ISSUE:
*Keynote address for DVCon 2006 - Skyscrapers and Chip Design
*Technical Program overview
*Cooleyís Bigwigs Panel
*DVCon Exhibitors
*Register now for DVCon 2006

Keynote Address - Skyscrapers and Chip Design

In his keynote, John Chilton, Senior Vice President and General Manager of the Solutions Group at Synopsys, Inc., shares insights on design productivity based on data gathered from real design projects. Many managers believe that the key to better productivity lies primarily in the quality of the tools, but thatís not the whole story. Join us to better understand the influencers of design productivity - those that you will recognize, and others that may surprise you.

DVCon Technical Program Overview provided by Gabe Moretti EDA

When the HDLCon executive committee decided to change the name of the conference to DVCon, they did so in order to provide a venue for the discussion of test bench languages in addition to design languages. This goal has been met, and test engineers can always find interesting topics when attending DVCon. But something subtler and yet more fundamental has happened to give the term DVCon even more meaning than what originally intended. It is now clear that verification and design are two inseparable tasks. The term design for verification has been used repeatedly in the last few years to indicate that designers must keep verification in mind when making design decisions. You can design equivalent circuits, one that is easy to verify and one that is very hard, if not impossible, to completely verify. So design and verification must be addressed on the same venue to permit tradeoffs in both approaches and tools. Much is being made today of DFM (Design for Manufacturing), but if we cannot verify the correctness of a design, we cannot manufacture it, at least not profitably. The constraints placed on designers continue to grow, in both number and complexity, and a fruitful exchange of ideas between designers and verification engineers will help diminish the complexity of the design task. DVCon aims to provide the opportunity for such an exchange. I hope to see you there.

John Cooley to moderate Bigwigs panel

Every year John Cooley gathers together bigwigs from most of the major and a few minor companies. He then surveys his 22,000 member ESNUG mailing list for edgy questions to ask his panelists. It makes for a very colorful discussion. All attendees are invited to a cocktail reception following the panel in the DVCon Exhibit Hall. Panelists will be announced prior to the conference and exhibition.

The panel will be held Thursday, February 23 from 3:30-5:00pm.

Free Exhibits and receptions at DVCon! February 22-23, 2006

The Exhibition will be open Wednesday, February 22 and Thursday, February 23 from 4pm-7pm at the DoubleTree Hotel San Jose. There are 19 exhibitors and 4 consultants. Come and see what is new in the industry and network with colleagues. There will be cocktail receptions both evenings beginning at 5:00pm. View a list of exhibitors and consultants.

Register Now to stay informed about the latest technology in Design Verification

The conference will be held February 22-24 and exhibition dates are February 22-23, 2006 at the DoubleTree Hotel in San Jose, California.  Wednesday tutorials, technical sessions, panels and embedded tutorials complete this dynamic 2006 program.

Book your hotel room for $135 per night at the DoubleTree Hotel San Jose, Group Code: DVC

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We look forward to seeing you soon!