HIGHLIGHTS IN THIS ISSUE:
*Letter from the General Chair
*Technical Program overview
*Verification Census by John Cooley
*DVCon Exhibitors
*Register now for DVCon 2006
*Sponsorship information

From Karen Bartleson, 2006 General Chair
We are part of an amazing industry in which chip producers continually increase product performance while reducing prices. Electronic merchandise keeps becoming progressively more complex,yet affordable for growing numbers of consumers. The year 2006 promises to introduce new technologies and new consumer products that will spur our economy forward. View entire letter from General Chair.

DVCon Technical Program Overview provided by Gabe Moretti EDA analysts have stated in the last few years that the costs of design verification amounts between 50 and 70% of the total projectcost. Designers and managers need to keep up-to-date with the latest products and methods available in order to identify possibleapproaches to diminishing these costs. DVCon is the only conferencein the EDA industry exclusively dedicated to design verification. Those attending the February 2006 conference will find a technicalprogram that offers papers and panels addressing both simulation and formal verification issues, and a full day of tutorials on the latest modeling and formal verification techniques.

Wednesday, February 22, Cadence, Mentor, and Synopsys are sponsoring tutorials. The first tutorial in the morning,sponsored by Cadence, will discuss how to deploy SystemVerilog, the latest IEEE modeling language standard, on your next project. Installing a new set of tools is always challenging and its success impacts not only the first design, but also the productivity ofdesign teams for months thereafter. Synopsys is sponsoring two tutorials, one in the morning titled "Using the Verification Methodology Manual (VMM) for SystemVerilog", and one in the afternoon that will cover SystemVerilog Assertions. The other afternoon tutorial, sponsored by Mentor Graphics, will deal with Transaction Level Modeling and Advanced Verification.

The technical program is divided in ten sections and concludes with three embedded tutorials on Friday afternoon. Topics to be covered include functional verification, formal verification techniques, a proposal for additional standardization work in both SystemVerilogand VHDL, as well as SystemC techniques.

Attendees will also hear John Chilton, Senior Vice President and General Manager of Synopsys' Solutions Group, deliver his keynote address at 2pm on Thursday, titled: "Skyscrapers and Chip Design". John Cooley will moderate the traditional, Bigwigs Panel on Thursday. Those who have attended the panel in the past know that it is everything but moderated! Another panel on Friday morning, moderated by Richard Goering, will explore "The Road to Actual Coverage".

The three intense days of DVCon will launch the winter EDA conference season and serve as a proper start to continuing education and new product discoveries for designers and EDA professionals alike. To view the complete technical program, please visit the DVCon website.

Verification Census from John Cooley
John Cooley compiled responses from 338 engineers on designverification tool use following the 2005 DVCon conference and exhibition. Read the entire report.

Exhibits at DVCon! February 22-23, 2006
The Exhibition along with the cocktail reception will be open for two days from 4pm-7pm. Come and see what is new in the industry and network with colleagues.

The exhibits and receptions are Free of charge!

Exhibitors include:

Aldec, Inc.,
Averant, Inc.,
Axiom Design Automation,
Shax Engineering and Systems,
Sutherland HDL, Inc.,
DiniGroup La Jolla, Inc.,
eInfochips, Inc., EVE,
Jasper Design Automation, Inc.,
Jeda Technologies,
Mentor Graphics Corp.,
Novas Software, Inc.,
Real Intent, Inc.,
Synopsys, Inc.,
Tharas Systems, Inc.

Register now to stay informed about the latest technology in Design Verification The conference will be held February 22-24 and exhibition dates are February 22-23, 2006 at the DoubleTree Hotel in San Jose, California.

Book your hotel room for $135 per night at the DoubleTree Hotel San Jose, Group Code: DVC

Corporate Sponsors
The following companies have generously contributed to the conference:

Cadence Design Systems, Inc.: Tutorial
Jasper Design Automation, Inc.: Conference Lanyards
Mentor Graphics Corp.: Tutorial and Thursday luncheon
Synopsys, Inc.: Tutorial and Thursday
Cocktail Reception

Other corporate sponsorships are still available. Contact Susie Horn at susie@mpassociates.com for information on how to promote your company at DVCon.

We look forward to seeing you in February!

Sincerely,

The DVCon 2006 Steering Committee