| It is understood that today's leading chip and system companies are facing ever more extreme design verification challenges. But verification isn't just about throwing more resources and CPUs at a simulation. It involves thinking differently about how to impact fundamental design quality. Decisions must be made about organizational structure (separate design/verification teams vs. designers who also verify), specifications, reuse, level of abstraction, how to work with EDA and IP vendors, etc.
This panel will explore why so much time is being spent in functional verification and discuss some of the incremental paradigm shifts taking place to address the verification challenge. What cultural and organizational changes have to take place to bring quality back to the forefront of design? Where is the measurable proof of quality? How much could we improve the overall quality level and reduce verification time to pull in schedules, and what would this take to do it?
Panelists:
- Gary Smith - Gartner Dataquest, San Jose, CA
Harry Foster - Jasper Design Automation, Inc., Mountain View, CA
Kevin Normoyle - Azul Systems, Mountain View, CA
Limor Fix - Intel Semiconductors Ltd., Hafia, Israel
Andrew Piziali - Verisity Design, Inc., Plano, TX
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