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DVCon is the premier conference on the usage of Hardware Description Languages (HDLs), and Hardware Verification Languages (HVLs) for the design and verification of electronic systems and integrated circuits. The focus of the conference is on specialized languages such as VHDL, PSL, Verilog, SystemVerilog, SystemC, SUPERLOG, e and VERA, as well as general purpose languages such as C, and C++. Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature, and reflect real life experiences in using HDLs and HVLs. |