Monday Tutorials
Tuesday Sessions
Wednesday Sessions
Keynote Address
Panel Sessions
Speakers/Presenters
Monday, March 1, 2004
DVCon is looking at ways to greatly reduce the cost for engineers to enroll in the tutorials. In this time of intense budgetary restrictions, DVCon is offering two sponsored tutorials included in the full conference registration fee. The minimal cost for Exhibit-only registrants is $50.00 per sponsored tutorial. Seating is Limited so register now!
Morning Tutorials
8:00 AM - 12:00 NOON

Tutorial 1 - Architecting Coverage Based Verification Flows
Presenter:
Ahmed Shahid - SiConcepts, Fremont, CA
Tutorial 2 - Using PSL with HDL for Formal and Dynamic Verification sponsored by:
Presenter:
Ben Cohen - VhdlCohen Training, Consultant, Rolling Hills Estates, CA
Tutorial 3 - Hardware and Software Co-Verification for ARM SoC Design
Presenter:
Jason Andrews - Axis Systems, Inc., Sunnyvale, CA
Afternoon Tutorials
1:00 PM - 5:00 PM
Tutorial 4 - Demonstrating and Effective Design-for-Verification Methodology with System Verilog
Presenters:
Tom Fitzpatrick - Synopsys, Inc., Groton, MA
Janick Bergeron - Synopsys, Inc., Ottawa, ON, Canada
Tutorial 5 - System Design and Verification using SystemC and SCV sponsored by:
Presenters:
Alan Fitch - Doulos Ltd., Ringwood, UK
Stuart Swan - Cadence Design Systems, Inc., San Jose, CA
Tutorial 6 - VHDL Transaction Based Verification
Presenter:
Jim Lewis - SynthWorks Design, Inc., Tigard, OR