Tutorial 6 • VHDL Transaction Based Verification

A transaction-based testbench codes a test in terms of interface actions rather than individual signal transitions. Modeling testbenches in this fashion allows the test writer to think at a higher level. Tests can be quickly constructed by using multiple transactions. The result is improved productivity and improved readability. A side-effect of increased readability is that the testbench is easier for system and software engineers to review and even perhaps contribute to the tests.

This tutorial shows how to create a system-level, transaction-based testbench using VHDL. A system-like environment is created by replacing each component of the system with either a bus functional model (BFM) or a full functional model (FFM). Transactions are created in a separate model called the transaction controller. A test consists of a sequence of transactions issued to one or more BFMs. Multiple tests are created by having multiple architectures of the transaction controller.

Although the implementation shown in this tutorial is coded in VHDL, the techniques can be applied to any hardware description or verification language.