Tutorial 4 • Demonstrating an Effective Design-for-Verification Methodology with SystemVerilog

This tutorial is presented in two parts. The first part will provide an overview of SystemVerilog, a single unified language providing advanced design and verification constructs to facilitate the description and verification of today's advanced SoC designs. The benefits and justification of integrating these features into a single language will be discussed.

The second part of the tutorial will present a proven strategy for using SystemVerilog to implement a coverage-driven random-based Design for Verification methodology. The methodology implements a layered, object-oriented testbench environment for constrained-random stimulus generation, self-checking transactors, and test automation at multiple levels of abstraction. We will also discuss how to use functional coverage as a feedback mechanism to know which particular tests or features have been automatically exercised. The environment can then be modified with a minimum of effort to target additional simulations at previously uncovered functionality. The role of the designer in including assertions and other indications of intent to enhance the verification will also be discussed. Detailed guidelines, templates and patterns will be presented so attendees will be immediately productive.