- See Synopsys’ Discovery Verification Platform at DVCon Booth #206
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- Delivering a New Level of Verification Excellence for Complex Chip Design
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- The Discovery™ Verification Platform is a unified environment providing high performance and productivity for complex SoC design verification. Discovery offers mixed-HDL, mixed-signal and system-level simulation supporting SystemVerilog, VHDL and SystemC. Advanced verification technologies are provided for assertions, code coverage, functional coverage, testbenches and formal analysis to rapidly identify all of your design bugs. Discovery raises verification to a new level of productivity enabling greater success for first-pass silicon of complex chip designs. Synopsys' offers a complete line of functional verification solutions that include VCS® HDL simulator, VCS MX mixed-HDL simulator, System Studio for system-level verification, LEDA® programmable RTL checker, Vera® testbench automation tool, Magellan™ hybrid RTL formal verification, DesignWare® verification IP, Formality® equivalence checker, NanoSim™ and HSPICE® for mixed-signal simulation.
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