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Tuesday, March 2, 2004
1:30 PM - 3:30 PM
Session 4 - Overcoming Challenging Verification Issues
4.1 Formally Verifying Clock Domain Crossing Jitter using Assertion-Based Verification
Tai Ly, Neil Hand, Chris Kwok - 0-In Design Automation, San Jose, CA

4.2 Designing a Safe Multi-Clock Chip with Clock Intent Verification
Jay Littlefield - Real Intent, Santa Clara, CA

4.3 Verification of Synchronization in Multi-Clock Domain SoC
 Ran Ginosa, Tsachy Kapshitz - Technion, Haifa, Israel
Richard Newton - @HDL, Inc., Milpitas, CA

4.4 Revitalized Techniques for SoC Verification
Prashant Rokade - Wipro Technologies, Bangalore, India
Naveen Bhoria - Texas Instruments, Bangalore, India
Thiyagarajan S. - Wipro Technologies, Bangalore, India
Gaurav Agrawal, Sunil Matange - Texas Instruments, Bangalore, India