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| Tuesday, March 2, 2004 |
1:30 PM - 3:30 PM
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| 3.1 Design and Debug with Advanced Languages: Challenges & Opportunities for SystemVerilog Stuart Suttherland - Sutherland HDL, Inc., Tualatin, OR Bassam Tabbara - Novas Software, Inc., San Jose, CA 3.2 IEEE 1076.6-200X: VHDL Synthesis Coding Styles for the Future 3.3 SystemVerilog from a Synthesis Perspective 3.4 The IEEE Verilog-2001 Simulation and Synthesis Tool Scoreboard - 2004 Update |
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