Panel 4 • The Impact of Language Evolution/Revolution on IC Design and Verification

New language standards promise improved designer efficiency by leveraging higher levels of abstraction for the design and verification of complex chips, especially large system-on-chip devices. Such efforts include SystemVerilog, SystemC and the proposed IEEE P1647 verification language. These languages provide design constructs for architectural, algorithmic and transaction-based modeling. They add an environment for automated testbench generation, while providing assertions to describe design functionality, including complex protocols, to drive verification using simulation or formal verification techniques. However, leveraging these new constructs in real methodologies involves a greater understanding of higher level programming techniques. Verifying these complex models requires significant forethought. Debugging abstract code can be complex and time consuming. This panel will explore the trade-offs that must be considered when adopting these new formats.

Panelists:
Dennis Brophy - Accellera, Wilsonville, OR
Victor Berman - Cadence Design Systems, Inc., Chelmford, MA
Dave Kelf - NovasSoftware Inc., San Jose, CA
Dan Smith - nVidia, Santa Clara, CA
Farhad Hayat - Synopsy, Inc., Mountain View, CA
Steve Glaser - Verisity Design, Inc., Mountain View, CA