Panel 3 • The Future of 3rd Party IP Verification: Evolution, or Revolution?

Verification of 3rd party design IP continues to be a significant problem. Latent bugs in design IP can cause unexpected delays in verification, or worse, respins of entire designs. Consumers of design IP often need to verify design IP before using it. But putting together a verification flow for design IP can be difficult.

Can we incrementally improve today's verification flows? Or do we need a radically different approach? What new technologies will address this issue? When does the cost of discovering yet another latent bug in design IP justify the cost of adopting new, perhaps unproven verification technology? When will EDA companies address this problem? Panelists representing design IP consumers, producers, and EDA companies will present their respective visions of the future of 3rd party design IP verification.

Panelists:
Axel Tillman - Novilit Inc., Marlborough, MA
Hiroaki Iwashita - Fujitsu Labs. Ltd., Kawasaki, Japan
Michael A. Beaver - iReady, Inc., Santa Clara, CA
Robert Fredieu - Zaiq Technologies, Inc., Woburn, MA
Bernard Deadman - Structured Design Verification, Inc., Austin, TX
Ashish Dixit - Tensilica, Inc., Santa Clara, CA