- Aldec will be highlighting advanced system-level verification methods using hardware acceleration, System Verilog, SystemC and Assertion-based Verification techniques at DVCon 2004. These features and many more are available on a single accelerated verification platform, Riviera-IPT. In addition, Aldec will be demonstrating new features and functionality of Riviera 2003.12, Active-HDL 6.2 all based on Aldec's industry leading mixed language VHDL and Verilog simulator.
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