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Wednesday, February 26, 2003
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| Full Day Tutorial |
8:00 AM - 5:00 PM
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Presenter:
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John R. Gilbert - Asgard ASIC, Inc. |
| Morning Tutorials |
8:00 AM - 12:00 PM
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| Tutorial 2 - Functional Verification with Specman Elite, Step-by-Step | |
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Zeev Kirshenbaum - Verisity Design, Inc. |
| Tutorial 3 - Finding More Bugs with VERA's Constraint-Driven Stimulus Generation | |
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Kelly Miller - Synopsys, Inc. |
| Tutorial 4 - The PSL/Sugar Assertion Language - A Language for all Seasons | |
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Presenters:
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Erich Marschner - Cadence Design Systems, Inc. Harry Foster - Verplex Systems, Inc. Yaron Wolfsthal - IBM Corp. Bernard Deadman - SDV Inc. |
| Afternoon Tutorials |
1:00 PM - 5:00 PM
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| Tutorial 5 - Transaction-based Modeling and Verification with SystemC | |
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Presenter:
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Kurt Schwartz - Willamette HDL, Inc. |
| Tutorial 6 - An Introduction to Smart Verification Using SystemVerilog | |
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Presenters:
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Tom Fitzpatrick - Synopsys, Inc. Mark Warren - Synopsys, Inc. |
| Tutorial 7 - The Design Flow - Linking Design, Verification, and Common Sense to Build Chips that Work | |
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Presenter:
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Frank Weiler - Apogee Consulting, Inc. |