| Wednesday, February 26, 2003 |
8:00 AM - 5:00 PM
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- Tutorial 1 - Practical Verilog for Chip-Level Verification
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| Presenter: John R. Gilbert - Asgard ASIC, Inc.
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This tutorial is deliberately NOT intended to be creatively brilliant! Instead, it is to be systematic, straight forward and useable for those who design and /or verify ASICs or FPGAs for a living. The intended audience is those who are quite hardware savvy, yet would like to increase their specific knowledge on the use of Verilog HDL for large design verification tasks. The tutorial covers the fundamental components to Chip-Level Verification using Verilog – a Chip-Level Verification approach, and use of Verilog HDL and Simulation to implement the Verification approach. Verilog HDL and Verilog Simulation are the only EDA tools with which attendees must be familiar. A contrived chip design is used throughout to illustrate the practical nature of both design verification approaches, as well as Verilog implementations. Tutorial coverage will be as follows:
- 1. Verification Strategies
2. Chip-Level Verification Overview
3. Developing Protocol-based Stimulus
4. Configuration Verification
5. SRAM Device Modeling
6. Peripheral Device Modeling
7. Operational Verification
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