Session 4 - Hardware Languages Trends and Techniques

4.2 Creating Relationally Placed Macros for FPGAs through VHDL
Steven Elzinga - Xilinx, Inc.

4.3 VHDL- The Verification Tool You Didn’t Know You Had
David Smith - Intel Corp.

4.4 Enhancements to VHDL's Packages
Jim Lewis - SynthWorks Design Inc.

4.6 The IEEE Verilog-2001 Simulation and Synthesis Tool Scoreboard
Clifford E. Cummings - Sunburst Design, Inc.

4.7 SystemVerilog 3.1, it's what the DAVEs in Your Company asked for
Stuart Sutherland - Sutherland HDL, Inc.