Session 3 - Verification Languages Trends and Techniques

3.2 Creating Useful Coding Guidelines for a Verification Environment
Ambar Sarkar - Paradigm Works

3.3 HDL and C/C++ Design Productivity in a Mixed Language Environment
Allan Zacharda - Model Technology, a Mentor Graphics Co.

3.4 Unified HDL Methodology Eases FPGA to ASIC Migration
Jill Wilker - Chip Express, Inc.

3.6 Installing Functional Coverage Metrics into VHDL Verification Simulations
Michael McKinney - Texas Instruments, Inc.

3.7 Verification of Skew and Jitter Tolerance and Compensation in High-Speed Interfaces
Alex Genusov, Steve Callahan - Zaiq Technologies