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| Monday, February 24, 2003 |
12:00 PM - 1:30 PM
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| Speaker: Aart de Geus - Chairman and CEO, Synopsys, Inc.
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| After almost 20 years of focusing on faster and faster simulation, moving from gates to RTL, we have reached a stage where we are now moving toward a new paradigm: "Design for Verification." Design for Verification will substantially improve capabilities and efficiencies in the verification process much as "design for test" did for the testing process by moving test concerns up from the post-design stage to the pre-design stage. In his keynote, Dr. de Geus will discuss the methodologies necessary to accomplish Design for Verification and the benefits it offers to designers grappling with ever-increasing complexity.
Aart de Geus is Chairman and CEO of Synopsys, Inc. Since co-founding Synopsys in 1986, he has grown it from a synthesis start-up to a global electronic design automation (EDA) leader for system-on-a-chip design. Dr. de Geus is a Fellow of the IEEE and the third ever recipient of IEEE’s Circuits and Systems (CAS) Society’s prestigious Industrial Pioneer Award. In 2001, Tsinghua University in Beijing honored Dr. de Geus the title of Guest Professor, placing him in the company of Nobel Prize laureates, scholars and visionaries in the technical community. He holds an MSEE from the Swiss Federal Institute of Technology and a Ph.D. in electrical engineering from Southern Methodist University. Dr. de Geus currently serves as the Chairman and Education Champion of the Silicon Valley Manufacturers Group. |
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