HDLCon 2001 Technical Program

Thursday Sessions
Friday Sessions
Tutorials
Keynote Addresses

9:00 am -

10:15 am
Session 1

Working with New VHDL and
Verilog HDL Standards
Session 2

Design Techniques and
Experiences Using HDLs
10:15 am -
10:45 am
Break
10:45 am -

11:35 am
Session 1 (cont.)

Working with New VHDL and
Verilog HDL Standards
Session 2 (cont.)

Design Techniques and
Experiences Using HDLs
11:45 am -
12:30 pm
Keynote Address
12:30 pm -
2:00 pm
Lunch
in the exhibit hall
2:00 pm -

3:15 pm
Session 3

SoC Design and
Reconfigurable Computing
Session 4

Design Verification
Languages and Techniques
3:15 pm -
3:45 pm
Break
3:45 pm -

5:00 pm
Session 3 (cont.)

SoC Design and
Reconfigurable Computing
Session 4 (cont.)

Design Verification
Languages and Techniques
5:00 pm -
7:00 pm
Cocktail Reception
in the exhibit hall