HDLCon 2001Technical Program

The 10th International HDL Conference Technical Program offers Tutorials, Technical Sessions, & Panels. System and Hardware Designers will be informed and educated about Verilog, VHDL and C/C++ for RTL and System level designs. Some of the topics covered are:

    • Verification tools and techniques including testbench generation;
    • System-level design environments including Verilog, VHDL, C/C++, SystemC, Superlog, Java
    • Design re-use and System-on-Chip
    • System-level simulation and hardware-software co-design
    • Language interoperability
    • HDLs for Mixed signal design

Just added Thursday Keynote Speaker Walden C. Rhines, Chairman and CEO, Mentor Graphics Corp.

We will also be featuring Keynote Panel: Design and Verification Languages: Are We Heading in the Right Direction This session will be moderated by John Cooley and is to include Panelists from leading FPGA and ASIC experts.