Session 4 • Design Verification: Languages and Techniques
	Chair: Stefen Boyd - Boyd Technology, Inc.		Room: Salons 1-3
Thursday March 1 • 2:00pm - 3:15pm		Thursday March 1 • 3:45pm - 5:00pm
4.1	Semi-Automated Testbench Generation for Communications Systems F. Gail Gray, Xin Qu, James R. Armstrong - Virginia Tech.	4.4	Verilog Transcendental Functions for Numerical Testbenches Mark G. Arnold, Colin Walter - UMIST Freddy Engineer - Xilinx
4.2	Assertions Targeting a Diverse Set of Verification Tools Harry Foster - Hewlett-Packard Co. Claudionor Coelho - Verplex Systems, Inc.	4.5	Growing Performance on a Simulation Farm John Willoughby - Cadence Design Systems, Inc.
4.3	Portable Automatic In-Situ Testbench Generation: A Case Study Lewis Sternberg, Janick Bergeron - Qualis Design Corp.	4.6	Pre-Silicon Validation versus Verification Aidan Herbert - iModl, Inc.