The International HDL Conference and Exhibition

HDLCon 2001 Technical Program

Thursday Sessions Friday Sessions Tutorials Keynote Addresses

Session 1 • Working with the new VHDL and Verilog HDL Standards

Chair: Jim Lewis - SynthWorks Design Inc.
Room: Salon C

Thursday March 1 • 8:30am - 9:45am Thursday March 1 • 10:15am - 11:05am

1.1 VHDL-2000: What's New
J. Bhasker - Cadence Design Systems, Inc.
Paul Menchini - Menchini & Associates 1.4 A Standard VHDL Memory Model for IEEE 1076.4-2000
Ekambaram Balaji - LSI Logic Corp.
Jose DeCastro - Quapix Consulting
Dennis Brophy - Model Technology Inc.

1.2 Verilog-2000 Behavioral and Synthesis Enhancements
Clifford E. Cummings - Sunburst Design, Inc. 1.5 Advanced ASIC Sign-Off Features of IEEE 1076.4-2000
Steve Wadsworth - American Microsystems, Inc.
Dennis Brophy - Model Technology Inc.

1.3 Extensions to the Synthesizable Subset for Verilog and VHDL
Lance Leong , Wolfgang Keil , Evan Rosser, Dongxiang Wu, Manish Mittal, Jay Adams - Synopsys, Inc.

Session 1 • Working with the new VHDL and Verilog HDL Standards
	Chair: Jim Lewis - SynthWorks Design Inc.		Room: Salon C
Thursday March 1 • 8:30am - 9:45am		Thursday March 1 • 10:15am - 11:05am
1.1	VHDL-2000: What's New J. Bhasker - Cadence Design Systems, Inc. Paul Menchini - Menchini & Associates	1.4	A Standard VHDL Memory Model for IEEE 1076.4-2000 Ekambaram Balaji - LSI Logic Corp. Jose DeCastro - Quapix Consulting Dennis Brophy - Model Technology Inc.
1.2	Verilog-2000 Behavioral and Synthesis Enhancements Clifford E. Cummings - Sunburst Design, Inc.	1.5	Advanced ASIC Sign-Off Features of IEEE 1076.4-2000 Steve Wadsworth - American Microsystems, Inc. Dennis Brophy - Model Technology Inc.
1.3	Extensions to the Synthesizable Subset for Verilog and VHDL Lance Leong , Wolfgang Keil , Evan Rosser, Dongxiang Wu, Manish Mittal, Jay Adams - Synopsys, Inc.